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Santa Clara, California - USD Full Time Posted: Friday, 10 August 2018
 
 
About the Position:
Our team is building key IPs in SSD controller, like NVMe IP and Flash controller IP. These IPs decide the functions and performance of SSD controller. Due to broad range of market targets, this team is required to make design flexible to support requirement from different market segments in a short period of time. This position will expose to this design technic and as well all algorithms like interface with host and NAND and advanced LDPC error correcting technology.
This position in particular is focusing on NVMe IP. The challenge of this position as senior staff design verification engineer is to have deep understanding of NVMe protocol and our NVMe IP architecture. Then you will need to design UVM-based test environment to cover as many corners as possible. You will need to involve to come up with test plan, coverage check points, coverage script, test bench architecture, sequence agent design, scoreboard design etc.
Responsibilities:
o Develop next generation SSD controller utilizing advanced digital technologies.
o UVM test bench development
o Perform Lint, CDC and LEC.
o Perform power and performance analysis for various types of IPs.
o Perform functional verification of design on block and system level.
o Review design documentation, description and information to internal and external customers.
Minimum Qualifications:
o MSEE with 2-5 years of experience in design verification
o Experience on UVM testbench
Preferred Qualifications:
o Knowledge of NVMe protocol
o Knowledge of NAND interface protocol (ONFI, Toggle)
o Knowledge of SSD controller architecture

Santa Clara, California, United States of America
Engineering
USD
Cavium
Cavium
JS2365_21300B142BFAA3A551AA65C42B309189/488567097
8/10/2018 1:45:39 PM

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